Method vcltzd_s64

vcltzd_s64(Int64)

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Dd,Dn,#0

Declaration

public static ulong vcltzd_s64(long a0)

Parameters

Type	Name	Description
Int64	a0	Int64 a0

Returns

Type	Description
UInt64	UInt64