Method vsubl_s16

vsubl_s16(v64, v64)

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL Vd.4S,Vn.4H,Vm.4H

Declaration

public static v128 vsubl_s16(v64 a0, v64 a1)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v64	a1	64-bit vector a1

Returns

Type	Description
v128	128-bit vector